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Data Sheet | Intel Enpirion Power Solutions: EM2130

Page 39

Figure 18: VIAs in The Power Pads

Recommendation 5: In order to better spread the current and the heat through the inner layers, arrays of

VIAs should be placed in the power pads. 10mils diameter is a good size for the plated in-pad VIAs. It is

critical that through VIAs should not be placed by any means elsewhere under the module; the non-pad

area around AGND is VIA keep out area.

Recommendation 6: All other signal and LDO decoupling capacitors should be placed as close as possible

to the terminal they are decoupling, while the AGND connection should be done through VIAs to the AGND

plane.

Figure 19: Backside Decoupling

All Signal Decoupling Go To The Bottom AGND Plane And Get Connected To The EM2130 Module

AGND Through The AGND In-PAD VIAs (Again, No Other VIAs Are Allowed In That Area)

Recommendation 7: Figure 20 also shows the 0Ω resistor that connects AGND to PGND. The

recommended connecting point, as shown, is to a quiet PGND  the output capacitors PGND.

Recommendation 8: Differential remote sense should be routed as much as possible as a differential pair,

on an inner layer, preferably shielded by a ground plane.

12873

April 10, 2020

Rev I

EVI-EM2COMIF 데이터시트(PDF) 39 Page - Intel Corporation