Preliminary Datasheet

LP6288

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LP6288

Version 0.1 JAN.-2018

Application Information(Continued)

Layout Guideline

The proper PCB layout and component placement are critical for all circuit. The careful attention should be

prevent electromagnetic interference (EMI) problems. Here are some suggestions to the layout of LP6280

design.

1. Connected all ground together with one uninterrupted ground plane, which include power ground and

analog ground.

2. The input capacitor should be located as closed as possible to the VIN and ground plane.

3. Minimize the distance of all traces connected to all the LX node, that the traces short and wide route to

obtain optimum efficiency.

4. All output capacitor must be closed to ground plane.

The ground terminal of COUT must be located as closed as possible to ground plane.

5. The exposed pad of the chip should be connected to ground plane for maximum thermal consideration..

VIN

BKI1

1

2

3

PGND

41

4

5

6

11 12 13 14 15 16

25

26

27

28

30

29

35

36

37

38

39

40

7

8

9

10

17 18 19 20

31

32

33

34

21

22

24

23

BKI1

RST

SDA

SCL

Addr

HVS

VLI

AGND

COMP

BKO3

PGND

BKLX3

BST3

BKI3

DRN

VGHM

VGH

DRVP

DRVN

Diode

VIN

AGND

PGND

PGND

PGND

Figure 9. Recommended PCB Layout Diagram