TDA7786 datasheet(20/54 Pages) STMICROELECTRONICS

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Function description

TDA7786, TDA7786M

20/54

DocID026122 Rev 5

Figure 8. I2S interface timing (transmitter)

Note:

The polarity of the signals and the data shift direction can be selected by configuration bits.

The audio SAI can be configured via software to be operating either in master or in slave

mode. The frame length is selectable as 16/32 bits per word, with 16/24 valid bits. Figure 9

shows the default setting of SAI for the 16-bit mode. Different settings of clock polarity, word

clock polarity, transmission mode (I2S mode) and data direction (either MSB or LSB first

transmission) are possible, and they can be changed through software. Supported

configurations are shown in Figure 10. Timing information for the protocols is detailed in

Figure 10.

Table 7. I2S interface timing (receiver)

Symbol

Parameter

Condition

Min.

Typ. Max. Unit

tCLK

Minimum Clock Cycle (CLK)

tCLKH

Minimum bit clock high time

tCLKL

Minimum bit clock low time

tWSS

Word-select setup time

slave mode

tWSH

Word-select hold time

slave mode

tWSD

Word-select delay

master mode

tDS

Data setup time

tDH

Data_hold time

Table 8. I2S interface timing (transmitter)

Symbol

Parameter

Condition

Min.

Typ. Max. Unit

tCLK

Minimum Clock Cycle (CLK)

tCLKH Minimum bit clock high time

tCLKL

Minimum bit clock low time

tWSS

Word-select setup time

slave mode

tWSH

Word-select hold time

slave mode

tWSD

Word-select delay

master mode

tDD

Data delay

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