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IS25LP016D-RMLA3:P 데이터시트(PDF) 11 Page - Integrated Silicon Solution, Inc

부품명 IS25LP016D-RMLA3:P
상세설명  SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE
PDF  114 Pages
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제조업체  ISSI [Integrated Silicon Solution, Inc]
홈페이지  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LP016D-RMLA3:P 데이터시트(HTML) 11 Page - Integrated Silicon Solution, Inc

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IS25LP016D
IS25WP016D
Integrated Silicon Solution, Inc.- www.issi.com
11
Rev. B10
03/09/2020
3. BLOCK DIAGRAM
Notes:
1. According to the P7 bit setting in Read Register, either HOLD# (P7=0) or RESET# (P7=1) pin can be selected.
2. SI and SO pins become bidirectional IO0 and IO1 respectively during Dual I/O mode and SI, SO, WP#, and
HOLD#/RESET# pins become bidirectional IO0, IO1, IO2, and IO3 respectively during Quad I/O or QPI mode.
3. In case of 16-pin SOIC and 24-ball TFBGA packages, dedicated RESET# function is supported without sharing with
HOLD# pin for the dedicated parts. See the Ordering Information for the dedicated RESET# pin
Control Logic
High Voltage Generator
I/O Buffers and
Data Latches
256 Bytes
Page Buffer
Y-Decoder
Status
Register
Address Latch &
Counter
Memory Array
CE#
SCK
WP#
(IO2)
SI
(IO0)
SO
(IO1)
HOLD# or RESET#
(IO3)
(1)
WP# (IO2)



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