ATXMEGA32E5 datasheet(13/153 Pages) MICROCHIP

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Data Sheet Complete

DS40002059A-page 13

ATxmega32E5/16E5/8E5

7. CPU

7.1

Features

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8/16-bit, high-performance AVR RISC CPU

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142 instructions

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Hardware multiplier

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32x8-bit registers directly connected to the ALU

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Stack in RAM

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Stack pointer accessible in I/O memory space

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Direct addressing of up to 16MB of program memory and 16MB of data memory

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True 16/24-bit access to 16/24-bit I/O registers

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Efficient support for 8-, 16-, and 32-bit arithmetic

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Configuration change protection of system-critical features

7.2

Overview

All AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and perform all

calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the program in

the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable Multilevel

Interrupt Controller” on page 34.

7.3

Architectural Overview

In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories and

buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one

instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to be

executed on every clock cycle. For details of all AVR instructions, refer to www.microchip.com.

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