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CS47L24 데이터시트(PDF) 87 Page - Cirrus Logic

부품명 CS47L24
상세설명  Low Power Audio Hub for Wearable Technology
PDF  256 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L24 데이터시트(HTML) 87 Page - Cirrus Logic

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CS47L24
Rev 4.1
87
The bracketed numbers in Figure 28,
e.g.,”(90h)” indicate the corresponding *_SRCn register setting for selection of that
signal as an input to another digital core function.
The register bits associated with the ASRCs are described in Table 22.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R3808
(0EE0h)
ASRC_EN
ABLE
3
ASRC2L_ENA
0
ASRC2 Left Enable
(Left ASRC channel from ASYNCCLK
domain to SYSCLK domain)
0 = Disabled
1 = Enabled
2
ASRC2R_ENA
0
ASRC2 Right Enable
(Right ASRC channel from ASYNCCLK
domain to SYSCLK domain)
0 = Disabled
1 = Enabled
1
ASRC1L_ENA
0
ASRC1 Left Enable
(Left ASRC channel from ASYNCCLK
domain to SYSCLK domain)
0 = Disabled
1 = Enabled
0
ASRC1R_ENA
0
ASRC1 Right Enable
(Right ASRC channel from ASYNCCLK
domain to SYSCLK domain)
0 = Disabled
1 = Enabled
R3809
(0EE1h)
ASRC_ST
ATUS
3
ASRC2L_ENA_S
TS
0
ASRC2 Left Enable Status
(Left ASRC channel from ASYNCCLK
domain to SYSCLK domain)
0 = Disabled
1 = Enabled
2
ASRC2R_ENA_S
TS
0
ASRC2 Right Enable Status
(Right ASRC channel from ASYNCCLK
domain to SYSCLK domain)
0 = Disabled
1 = Enabled
1
ASRC1L_ENA_S
TS
0
ASRC1 Left Enable Status
(Left ASRC channel from ASYNCCLK
domain to SYSCLK domain)
0 = Disabled
1 = Enabled
0
ASRC1R_ENA_S
TS
0
ASRC1 Right Enable Status
(Right ASRC channel from ASYNCCLK
domain to SYSCLK domain)
0 = Disabled
1 = Enabled
R3810
(0EE2h)
ASRC_RA
TE1
14:11
ASRC_RATE1
[3:0]
0000
ASRC Sample Rate select for SYSCLK
domain
0000 = SAMPLE_RATE_1
0001 = SAMPLE_RATE_2
0010 = SAMPLE_RATE_3
All other codes are Reserved.
The selected sample rate is valid in the
range 8kHz to 48kHz.
The ASRC_IN1L_SRC and
ASRC_IN1R_SRC registers should be set
to 00h before ASRC_RATE1.



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