ASM2I99447 datasheet(8/14 Pages) ALSC

8 / 14 page

May 2005

ASM2I99447

rev 0.3

3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer

8 of 14

Notice: The information in this document is subject to change without notice.

CCLK

VCC

VCC ÷2

GND

tP(LH)

tP(HL)

VCC

VCC ÷2

GND

Figure 6. Propagation Delay (tPD) Test Reference

tSK(LH)

tSK(HL)

VCC

VCC ÷2

GND

VCC

VCC ÷2

GND

The pin-to-pin skew is defined as the worst case

difference in propagation between any similar delay path

within a single device

Figure 7. Output–to–Output Skew tSK(LH, HL)

CCLK

VCC

VCC ÷2

GND

tP(LH)

tP(HL)

VCC

VCC ÷2

GND

tSK(P) =| tPHL - tPHL |

Figure 8. Output Pulse Skew (tSK(P) Test

VCC

VCC ÷2

GND

DC (tP ÷T0 Χ 100%)

The time from the output controlled edge to the

non-controlled edge, divided by the time output

controlled edge, expressed as a percentage.

Figure 9. Output Duty Cycle (DC)

VCC = 3.3V VCC = 2.5V

2.4

1.8V

0.5

0.6V

Figure 10. Output Transition Time Test Reference

TN + 1

TJIT(CC) = |TN -TN + 1|

The variation in cycle time of a single between adjacent

cycles, over a random sample of adjacent cycle pairs

Figure 11. Cycle–to–Cycle Jitter Reference

CCLK

PCLK

VCC

VCC ÷2

GND

VCC

VCC ÷2

GND

CLK_STOP

Figure 12. Setup and Hold Time (tS, tH) Test Reference

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