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FDMS3602S 데이터시트(PDF) 12 Page - ON Semiconductor |
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FDMS3602S 데이터시트(HTML) 12 Page - ON Semiconductor |
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12 / 15 page ![]() Figure 30. Shows the Power Stage in a buck converter topology 2. Recommended PCB Layout Guidelines As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2), should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout proce- dure is discussed below to maximize the electrical and thermal performance of the part. Figure 31. Recommended PCB Layout www.onsemi.com 12 |
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