DF69 datasheet(4/106 Pages) PADAUK

4 / 106 page

DF69

DC Fan Controller

5-10. WatchDog Timer................................................................................................................40

5-11. Interrupt .............................................................................................................................41

5-12. Power-Save and Power-Down ...........................................................................................43

5-12-1. Power-Save mode (“stopexe”) ...............................................................................43

5-12-2. Power-Down mode (“stopsys”) ...............................................................................44

5-12-3. Wake-up ................................................................................................................45

5-13. IO Pins...............................................................................................................................46

5-14. Reset and LVD (Low Voltage Detection)............................................................................47

5-14-1. Reset .....................................................................................................................47

5-14-2. LVD reset...............................................................................................................47

5-15. Hall Comparator.................................................................................................................48

5-16. Analog-to-Digital Conversion (ADC) module ......................................................................49

5-16-1. The input requirement for AD conversion ...............................................................50

5-16-2. Select the ADC bit resolution .................................................................................50

5-16-3. ADC clock selection ...............................................................................................50

5-16-4. AD conversion........................................................................................................51

5-16-5. Configure the analog pins ......................................................................................51

5-16-6. Using the ADC .......................................................................................................52

5-17 10-BIT PWM generator .......................................................................................................53

5-17-1. PWM Waveform.....................................................................................................53

5-17-2. Hardware and Timing Diagram ..............................................................................53

5-17-3. Equations for 10-bit PWM Generator .....................................................................54

5-18 Input Pulse Capture ............................................................................................................55

5-19 PWM Protection..................................................................................................................56

5-20 Multiplier .............................................................................................................................57

5-21. General Purpose Comparator ............................................................................................58

5-21-1. General Purpose Comparator Hardware Diagram..................................................58

5-21-2. Analog Inputs .........................................................................................................59

5-21-3. Internal reference voltage (Vinternal R) .......................................................................59

5-21-4. Synchronizing General Purpose Comparator Output to Timer2..............................62

5-21-5. Using the general purpose comparator ..................................................................62

5-21-6. Using the comparator and band-gap 1.20V ............................................................63

6. IO Registers.......................................................................................................................... 64

6-1. ACC Status Flag Register (flag), IO address = 0x00 ............................................................64

6-2. FPP unit Enable Register (fppen), IO address = 0x01..........................................................64

6-3. Stack Pointer Register (sp), IO address = 0x02 ...................................................................64

6-4. Clock Mode Register (clkmd), IO address = 0x03 ................................................................65

6-5 Register Option Register (rop), IO address = 0x3e ...............................................................65

Page 4 of 106

PDK-DS-DF69_V003 – Apr. 18, 2018

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