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CS4614 데이터시트(PDF) 16 Page - Cirrus Logic

부품명 CS4614
상세설명  CrystalClear SoundFusion PCI Audio Accelerator
PDF  24 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS4614 데이터시트(HTML) 16 Page - Cirrus Logic

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CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM
DS292PP3
CS4614
CrystalClear™ SoundFusion™ PCI Audio Accelerator
EEPROM INTERFACE
The EEPROM configuration interface allows the
connection of an optional external EEPROM de-
vice to provide power-up configuration informa-
tion. The external EEPROM is not required for
proper operation; however, in some applications
power-up configuration settings other than the de-
fault values may be required to support specific
Operating System compatibility requirements.
After a hardware reset, an internal state machine in
the CS4614 will automatically detect the presence
of an external EEPROM device and load the Sub-
system ID and Subsystem Vendor ID fields, along
with two bytes of general configuration informa-
tion, into internal registers. At power-up, the
CS4614 will attempt to read from the external de-
vice, and will check the data received from the de-
vice for a valid signature header. If the header data
is invalid, the data transfer is aborted. After power-
up, the host can read or write from/to the EEPROM
device by accessing specific registers in the
CS4614. Cirrus Logic provides software to read
and write the EEPROM.
The two-wire interface for the optional external
EEPROM device is depicted in Figure 11. During
data transfers, the data line (EEDAT) can change
state only while the clock signal (EECLK) is low.
A state change of the data line while the clock sig-
nal is high indicates a start or stop condition to the
EEPROM device.
+5 V
DSP
1 nF
1
9
8
4
5
2
10
7
14
12
15
1 nF
5.6 nF
5.6 nF
2.2 k
Ω
2.2 k
Ω
MIDIIN
MIDIOUT
JAB2
JBB2
JACY
JBCY
JBCX
JACX
JBB1
JAB1
3
11
13
6
1 nF
1 nF
2.2 k
Ω
2.2 k
Ω
5.6 nF
5.6 nF
4.7 k
Ω
4.7 k
Ω
4.7 k
Ω
4.7 k
Ω
4.7 k
Ω
Figure 10. Joystick Logic
SLIMD SP
Core
EEDAT
EECLK
4.7 k
Ω
2-wire
Serial
EEPROM
Figure 11. External EEPROM Connection



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