47L16 datasheet(18/40 Pages) MICROCHIP

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47L04/47C04/47L16/47C16

DS20005371C-page 18

 2015-2016 Microchip Technology Inc.

2.4.3

CONTROL REGISTER WRITE

OPERATION

When the Control registers are selected and the R/W

bit in the control byte is set to ‘0’, a write operation is

selected and the next byte received is interpreted as

the register address. The Most Significant address bits

are transferred first, followed by the less significant

bits. The register address is decoded as soon as it is

received and has no effect on future operations.

The register address must be a valid Control register

address listed in Table 2-4, otherwise the 47XXX will

not acknowledge the address, the current operation

will be terminated, and any data transmitted on the

SDA line will be ignored until a new operation is begun

with a Start condition.

After receiving the Acknowledge signal from the

47XXX following the register address, the master will

transmit the data byte to be written to the addressed

If the data byte is valid, the 47XXX acknowledges

again and the master generates a Stop condition.

For a STATUS register write operation, any data byte

value is valid. However, for COMMAND register write

operations, only the commands listed in Table 2-6 are

valid. If a different command value is received, the

47XXX will not acknowledge the command, the

current operation will be terminated, and any data

transmitted on the SDA line will be ignored until a new

operation is begun with a Start condition.

FIGURE 2-9:

CONTROL REGISTER WRITE

2.4.4

CONTROL REGISTER READ

OPERATION

When the Control registers are selected and the R/W

bit in the control byte is set to ‘1’, a read operation is

selected. For read operations, the register address is

not transmitted. Since the COMMAND register is

write-only, all Control register read operations access

the STATUS register.

During read operations, the master device generates

the Acknowledge bit after each data byte, and it is this

bit which determines whether the operation will con-

tinue or end. A ‘0’ (Acknowledge) bit requests more

data and continues the read, while a ‘1’ (No Acknowl-

edge) bit ends the read operation.

Upon receipt of the control byte with the R/W bit set to

‘1’, the 47XXX issues an Acknowledge and transmits

the 8-bit STATUS register value. The master will not

acknowledge the transfer, but does generate a Stop

condition and the 47XXX discontinues transmission

(Figure 2-10).

FIGURE 2-10:

CONTROL REGISTER

READ

Note 1:

When writing to the COMMAND register,

the master must send exactly one data

byte. If additional data bytes are sent,

then the 47XXX will not acknowledge the

data bytes and will abort the operation.

Multiple data bytes are allowed when

writing to the STATUS register. The last

data byte received will be written.

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

Address

Byte

Data

S 00 11

TWC(1)

TSTORE(1)

TRECALL(1)

Note 1:

After the Stop condition, a delay must be observed for the command to execute: TWC for STATUS register writes,

TSTORE for Software Store commands, and TRECALL for Software Recall commands.

Note:

If the master acknowledges the data

byte, the 47XXX will retransmit the 8-bit

STATUS register value.

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

01 AA

Byte

STATUS

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