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FS32K112BHTXVLLTR 데이터시트(PDF) 20 Page - NXP Semiconductors

부품명 FS32K112BHTXVLLTR
상세설명  Low-power Arm Cortex-M4F/M0 core with excellent energy efficiency
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Table 12. Power mode transition operating behaviors for S32K14xW series
Symbol
Description
Min.
Typ.
Max.
Unit
tPOR
After a POR event, amount of time from the point VDD
reaches 3.13 V to execution of the first instruction
across the operating temperature range of the chip.
—
TBD
—
μs
VLPS → RUN
TBD
—
TBD
μs
STOP1 → RUN
TBD
TBD
TBD
μs
STOP2 → RUN
TBD
TBD
TBD
μs
VLPR → RUN
TBD
—
TBD
μs
VLPR → VLPS
TBD
TBD
TBD
μs
VLPS → VLPR
TBD
TBD
TBD
μs
RUN → Compute operation
TBD
TBD
TBD
μs
RUN → STOP1
TBD
TBD
TBD
μs
RUN → STOP2
TBD
TBD
TBD
μs
RUN → VLPS
TBD
TBD
TBD
μs
RUN → VLPR
TBD
TBD
TBD
μs
VLPS → Asynchronous DMA Wakeup
TBD
TBD
TBD
μs
STOP1 → Asynchronous DMA Wakeup
TBD
TBD
TBD
μs
STOP2 → Asynchronous DMA Wakeup
TBD
TBD
TBD
μs
Pin reset → Code execution
—
TBD
—
μs
4.7 Power consumption
The following table shows the power consumption targets for the device in various mode
of operations. Attached S32K1xx_Power_Modes _Configuration.xlsx details the modes
used in gathering the power consumption data stated in the following table Table 13. For
full functionality refer to table: Module operation in available power modes of the
Reference Manual
.
General
S32K1xx Data Sheet, Rev. 12, 02/2020
20
NXP Semiconductors



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