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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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IIS2DLPC 데이터시트(PDF) 29 Page - STMicroelectronics |
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IIS2DLPC 데이터시트(HTML) 29 Page - STMicroelectronics |
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29 / 69 page  DocID031788 Rev 4 29/69 IIS2DLPC Digital main blocks 69 5 Digital main blocks 5.1 Block diagram of filters Figure 7. Accelerometer chain Referring to Figure 7, the first block is the Low-Pass Filter 1 (LPF1) whose behavior is a function of the actual ODR and mode selected in CTRL1 (20h). The signal is then downsampled and can be either directly sent to the output registers or to the Low-Pass Filter 2 (LPF2) or High-Pass-Filter (HP) using the BW_FILT[1:0] bits and FDS bit in CTRL6 (25h). In the low-pass path, it is possible to apply a user offset determined by the X_OFS_USR (3Ch), Y_OFS_USR (3Dh), Z_OFS_USR (3Eh) register values and the USR_OFF_W bit in CTRL7 (3Fh) and send the result to the output using the USR_OFF_ON_OUT bit in CTRL7 (3Fh). In the high-pass path, it is possible to use the high-pass filter reference mode (HP) using the HP_REF_MODE bit in CTRL7 (3Fh). |
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