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ADGM1004JCPZ-R2 데이터시트(PDF) 7 Page - Analog Devices

부품명 ADGM1004JCPZ-R2
상세설명  0 Hz/DC to 13 GHz, 2.5 kV HBM ESD, SP4T, MEMS Switch with Integrated Driver
PDF  32 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
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ADGM1004JCPZ-R2 데이터시트(HTML) 7 Page - Analog Devices

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Data Sheet
ADGM1004
Rev. D | Page 7 of 32
TIMING CHARACTERISTICS
VDD = 3.0 V to 3.6 V, GND = 0 V, and all specifications TMIN to TMAX = 0°C to +85°C, unless otherwise noted.
Table 2.
Parameter
Description
Limit at TMIN
Limit at TMAX
Unit
t1
SCLK period
100
ns
t2
SCLK high pulse width
45
ns
t3
SCLK low pulse width
45
ns
t4
CS falling edge to SCLK active edge
25
ns
t5
Data setup time
20
ns
t6
Data hold time
20
ns
t7
SCLK active edge to CS rising edge
25
ns
t8
CS falling edge to SDO data available
20
ns
t91
SCLK falling edge to SDO data available
40
ns
t10
CS rising edge to SDO returns to high impedance
25
ns
t11
CS high time between SPI commands
100
ns
t12
SCLK edge rejection to CS falling edge
25
ns
t13
CS rising edge to SCLK edge rejection
25
ns
1 Measured with a 20 pF load, t9 determines the maximum SCLK frequency when the SDO pin is used.



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