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ADGS1414DBCCZ 데이터시트(PDF) 23 Page - Analog Devices |
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ADGS1414DBCCZ 데이터시트(HTML) 23 Page - Analog Devices |
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23 / 28 page ![]() Data Sheet ADGS1414D Rev. 0 | Page 23 of 28 APPLICATIONS INFORMATION SYSTEM CHANNEL DENSITY The ADGS1414D feature set allows for large system channel density. These features include route through pins for the digital signals and power supplies, as well as integrated passive components. Route Through Pins When multiple ADGS1414D devices are used in a system, the route through pins allow for a greater channel density layout. The route through pins enable the passing of power supplies and digital lines between devices with ease. The VDD, RESET/VL, and GND power lines, as well as the SCLK, CS, SDI, and SDO digital lines, are available on both the top and bottom pins of the package. These route through pins simplify PCB routing and reduce the need for vias when connecting many ADGS1414D devices together. Figure 45 shows an example layout where the route through pins on four ADGS1414D devices configured in daisy-chain mode are used to reduce the overall size of the layout. Integrated Passive Components Note the lack of external passive components in the layout in Figure 45. The ADGS1414D has integrated decoupling capacitors for the VDD, VSS, and RESET/VL power supplies. Therefore, the need for external decoupling capacitors is eliminated, reducing the total system footprint of the ADGS1414D. If additional decoupling is required for extremely noise sensitive applications, add an external decoupling capacitor. Figure 21 shows the AC PSRR performance with and without external decoupling capacitors. Figure 45. Layout Example Showing the Use of the Route Pins and the Elimination of External Passive Components VDD GND RESET/VL SDO SCLK CS VDD GND RESET/VL SDO SCLK CS |
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