PCF8536AT datasheet(28/54 Pages) NXP

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PCA85276

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Product data sheet

Rev. 3 — 12 November 2018

28 of 54

NXP Semiconductors

PCA85276

Automotive 40 x 4 LCD driver

7.5 I2C-bus controller

The PCA85276 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or

transmit data to an I2C-bus master receiver. The only data output from the PCA85276 are

the acknowledge signals of the selected devices. Device selection depends on the

I2C-bus slave address, on the transferred command data and on the hardware

subaddress.

In single device applications, the hardware subaddress inputs A0 and A1 are normally

tied to VSS which defines the hardware subaddress 0. In multiple device applications A0

and A1 are tied to VSS or VDD using a binary coding scheme, so that no two devices with a

common I2C-bus slave address have the same hardware subaddress.

7.6 Input filters

To enhance noise immunity in electrically adverse environments, RC low-pass filters are

provided on the SDA and SCL lines.

7.7 I2C-bus protocol

Two I2C-bus slave addresses (0111 000 and 0111 001) are used to address the

PCA85276. The entire I2C-bus slave address byte is shown in Table 16.

The PCA85276 is a write-only device and will not respond to a read access, therefore bit 0

should always be logic 0. Bit 1 of the slave address byte that a PCA85276 will respond to,

is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1).

Having two reserved slave addresses allows the following on the same I2C-bus:

• Up to 8 PCA85276 for very large LCD applications

• The use of two types of LCD multiplex drive modes

The I2C-bus protocol is shown in Figure 20. The sequence is initiated with a START

condition (S) from the I2C-bus master which is followed by one of the two possible

PCA85276 slave addresses available. All PCA85276 whose SA0 inputs correspond to

bit 0 of the slave address respond by asserting an acknowledge in parallel. This I2C-bus

transfer is ignored by all PCA85276 whose SA0 inputs are set to the alternative level.

Table 16.

I2C slave address byte

Slave address

Bit

MSB

LSB

SA0

R/W

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