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74LS194 데이터시트(PDF) 2 Page - ON Semiconductor |
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74LS194 데이터시트(HTML) 2 Page - ON Semiconductor |
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2 / 8 page ![]() SN74LS194A http://onsemi.com 2 CONNECTION DIAGRAM DIP (TOP VIEW) Mode Control Inputs Parallel Data Inputs Serial (Shift Right) Data Input Serial (Shift Left) Data Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Parallel Outputs S0, S1 P0 – P3 DSR DSL CP MR Q0 – Q3 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. HIGH LOW (Note a) LOADING PIN NAMES 14 13 12 11 10 9 1234 5 6 7 16 15 8 VCC MR Q0 Q1 Q2 Q3 S1 CP S0 DSR P0 P1 P2 P3 DSL GND |
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