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SN74LS299 데이터시트(PDF) 2 Page - ON Semiconductor

부품명 SN74LS299
상세설명  LOW POWER SCHOTTKY
PDF  8 Pages
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제조업체  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

SN74LS299 데이터시트(HTML) 2 Page - ON Semiconductor

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SN74LS299
http://onsemi.com
2
CONNECTION DIAGRAM DIP (TOP VIEW)
Clock Pulse (Active Positive–Going Edge) Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Parallel Data Input or
Parallel Output (3–State)
3–State Output Enable (Active LOW) Inputs
Serial Outputs
Asynchronous Master Reset (Active LOW) Input
Mode Select Inputs
CP
DS0
DS7
I/On
OE1, OE2
Q0, Q7
MR
S0, S1
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
0.5 U.L.
10 U.L.
0.5 U.L.
1 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
0.25 U.L.
5 U.L.
0.25 U.L.
0.5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
mA HIGH/1.6 mA LOW.
HIGH
LOW
(Note a)
LOADING
PIN NAMES
18
17
16
15
14
13
12
3
4
5
6
7
20
19
8
VCC
S0
S1
Ds7
Q7
I/O7
I/O3
I/O5
I/O1
OE1 OE2 I/O6 I/O4 I/O2 I/O0 Q0
910
MR GND
12
11
CP
DS0
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
S1
S0
DS0
CLOCK
Q0
MR
OE1
OE2
D
CLR
Q
CK
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DS7
Q7
VCC = PIN 20
GND = PIN 10
= PIN NUMBERS
14
1
2
6
7
3
8
4
5
9
11
12
13
15
16
17
18
19
D
CLR
Q
CK
D
CLR
Q
CK
D
CLR
Q
CK
D
CLR
Q
CK
D
CLR
Q
CK
D
CLR
Q
CK
D
CLR
Q
CK
LOGIC DIAGRAM



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