11 Layout

11.1 Layout guidelines

Robust and reliable bus node design often requires the use of external transient protection devices in order to

protect against surge transients that may occur in industrial environments. Since these transients have a wide

frequency bandwidth (from approximately 3 MHz to 300 MHz), high-frequency layout techniques should be

applied during PCB design.

1. Place the protection circuitry close to the bus connector to prevent noise transients from propagating across

the board.

path of least impedance and not the path of least resistance.

3. Place F_SET components near the pin to keep capacitance load below recommended value

4. Use a pull up or down resistor on mode to set a default state

UART and/or controller ICs on the board.

minimize effective via inductance.

7. Use 1-kΩ to 10-kΩ pull-up and pull-down resistors for enable lines to limit noise currents in theses lines

during transient events.

8. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified

maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the

transceiver and prevent it from latching up.

9. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide

varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient

blocking units (TBUs) that limit transient current to less than 1 mA.

11.2 Layout Example

MCU

Via to GND

THVD8010

R

R

C

2

1

2

3

MODE

F_SET

D

B

A

GND

R

R

C

C

Figure 11-1. Layout Example (OOK)

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THVD8010

SLLSFK4 – NOVEMBER 2020

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