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74LS298 데이터시트(PDF) 4 Page - ON Semiconductor

부품명 74LS298
상세설명  LOW POWER SCHOTTKY
PDF  8 Pages
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제조업체  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

74LS298 데이터시트(HTML) 4 Page - ON Semiconductor

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DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK
Input Clamp Diode Voltage
– 0.65
– 1.5
V
VCC = MIN, IIN = – 18 mA
VOH
Output HIGH Voltage
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VO
Output LOW Voltage
0.25
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
VIN =VIL or VIH
VOL
Output LOW Voltage
0.35
0.5
V
IOL = 8.0 mA
VIN = VIL or VIH
per Truth Table
I
Input HIGH Current
20
µA
VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
0.1
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
– 0.4
mA
VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
–20
– 100
mA
VCC = MAX
ICC
Power Supply Current
21
mA
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tPLH
Propagation Delay,
18
27
ns
VCC = 5.0 V,
PLH
tPHL
gy
Clock to Output
21
32
ns
CC
CL = 15 pF
AC SET-UP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tW
Clock Pulse Width
20
ns
ts
Data Setup Time
15
ns
ts
Select Setup Time
25
ns
VCC = 5.0 V
th
Data Hold Time
5.0
ns
th
Select Hold Time
0
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.



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