iCE40 LP/HX Family

Data Sheet

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32

FPGA-DS-02029-3.5

Parameter

Description

Device

Min.

Max.

Units

Clock to Output - PIO Output Register

iCE40LP1K

—

2.20

ns

iCE40LP4K

—

2.30

ns

iCE40LP8K

—

2.30

ns

Clock to Data Setup - PIO Input Register

iCE40LP1K

5.23

—

ns

iCE40LP4K

6.13

—

ns

iCE40LP8K

6.13

—

ns

Clock to Data Hold - PIO Input Register

iCE40LP1K

–0.90

—

ns

iCE40LP4K

–0.80

—

ns

iCE40LP8K

–0.80

—

ns

Notes:

1.

Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85 °C and 1.14 V.

Other operating conditions can be extracted from the iCECube2 software.

2.

General I/O timing numbers based on LVCMOS 2.5, 0 pf load.

3.

Supported on devices with a PLL.