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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HT46C23 데이터시트(PDF) 13 Page - Holtek Semiconductor Inc |
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HT46C23 데이터시트(HTML) 13 Page - Holtek Semiconductor Inc |
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13 / 48 page  HT46R23/HT46C23 Rev. 1.60 13 May 3, 2004 When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will en- able the SST delay. The functional unit chip reset status are shown below. An extra option load time delay is added during system reset (power-up, WDT time-out at normal mode or RES reset). PC 000H Interrupt Disable WDT Clear. After master reset, WDT begins counting Timer/Event Counter Off Input/Output Ports Input mode SP Points to the top of the stack The registers states are summarized in the following table. Register Reset (Power On) WDT Time-out (Normal Operation) RES Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* TMRL xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMRH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMRC 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu Program Counter 000H 000H 000H 000H 000H MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu INTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu INTC1 ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---u ---u PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PC ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---u uuuu PCC ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---u uuuu PD ---- --11 ---- --11 ---- --11 ---- --11 ---- --uu PDC ---- --11 ---- --11 ---- --11 ---- --11 ---- --uu PWM0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PWM1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu HADR xxxx xxx- xxxx xxx- xxxx xxx- xxxx xxx- uuuu uuu- HCR 0--0 0--- 0--0 0--- 0--0 0--- 0--0 0--- u--u u--- HSR 100- -0-1 100- -0-1 100- -0-1 100- -0-1 uuu- -u-u HDR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRL xx-- ---- xx-- ---- xx-- ---- xx-- ---- uuuu ---- ADRH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADCR 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu ACSR 1--- --00 1--- --00 1--- --00 1--- --00 u--- --uu Note: ²*² stands for warm reset ²u² stands for unchanged ²x² stands for unknown |
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