XIO2001IPNP datasheet(87/144 Pages) TI

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XIO2001

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SCPS212I – MAY 2009 – REVISED JANUARY 2016

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8.4.75 Serial IRQ Status Register

This register indicates when a level mode IRQ is signaled on the serial IRQ stream. After a level mode IRQ is

signaled, a write-back of 1b to the asserted IRQ status bit re-arms the interrupt. IRQ interrupts that are defined

as edge mode in the serial IRQ edge control register are not reported in this status register. See Table 58 for a

complete description of the register contents.

PCI register offset:

E4h

Read/Clear

Default value:

0000h

BIT NUMBER

RESET STATE

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

Table 58. Serial IRQ Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15(1)

IRQ15

RCU

IRQ 15 asserted. This bit indicates that the IRQ15 has been asserted.

0 = Deasserted

1 = Asserted

14(1)

IRQ14

RCU

IRQ 14 asserted. This bit indicates that the IRQ14 has been asserted.

0 = Deasserted

1 = Asserted

13(1)

IRQ13

RCU

IRQ 13 asserted. This bit indicates that the IRQ13 has been asserted.

0 = Deasserted

1 = Asserted

12(1)

IRQ12

RCU

IRQ 12 asserted. This bit indicates that the IRQ12 has been asserted.

0 = Deasserted

1 = Asserted

11(1)

IRQ11

RCU

IRQ 11 asserted. This bit indicates that the IRQ11 has been asserted.

0 = Deasserted

1 = Asserted

10(1)

IRQ10

RCU

IRQ 10 asserted. This bit indicates that the IRQ10 has been asserted.

0 = Deasserted

1 = Asserted

9(1)

IRQ9

RCU

IRQ 9 asserted. This bit indicates that the IRQ9 has been asserted.

0 = Deasserted

1 = Asserted

8(1)

IRQ8

RCU

IRQ 8 asserted. This bit indicates that the IRQ8 has been asserted.

0 = Deasserted

1 = Asserted

7(1)

IRQ7

RCU

IRQ 7 asserted. This bit indicates that the IRQ7 has been asserted.

0 = Deasserted

1 = Asserted

6(1)

IRQ6

RCU

IRQ 6 asserted. This bit indicates that the IRQ6 has been asserted.

0 = Deasserted

1 = Asserted

5(1)

IRQ5

RCU

IRQ 5 asserted. This bit indicates that the IRQ5 has been asserted.

0 = Deasserted

1 = Asserted

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