XIO2001IPNP datasheet(119/144 Pages) TI

119 / 144 page

XIO2001

EXT_ARB_EN

REQ[5:1]

GNT0

REQ0

VCCP

3.3 V

GNTx

GNTy

REQx

REQy

External Arbiter

GNT

REQ

PCI Device

PCI Bus

119

XIO2001

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SCPS212I – MAY 2009 – REVISED JANUARY 2016

Product Folder Links: XIO2001

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Typical Application (continued)

Figure 26. External Arbiter Connections

9.2.1.2.1.1

Bus Parking

Because of the shared bus nature of PCI, it is required that if the bus is idle at a given time that some device on

the bus must drive some signals to stable states. These signals are the address/data lines, the command/byte

enables, and a valid parity. If no devices are requesting use of the bus, it is the responsibility of the arbiter to

assign ownership of the bus so that the bus signals are never floating while in idle states.

If the XIO2001 internal arbiter is enabled then there are two modes supported for bus parking. The default mode

for bus parking is for the arbiter to continue to assert GNT for the last bus master. In this mode once a device

has completed its transaction, the arbiter will continue to assert the GNT for that bus master and that device is

required to drive a stable pattern onto the required signals. This will continue until another device requests use of

the bus resulting in the arbiter removing GNT from the current bus owner grants it to the new requestor.

Alternatively, the XIO2001 can be configured to self-park. In this mode if no other devices have their REQ

asserted, the XIO2001 will remove GNT from the current bus owner and drive a stable pattern onto the required

lines.

It is suggested that implementations use the default mode of bus parking. The PCI Specification recommends

leaving the current GNT signal asserted if no devices are asserting REQ. Some PCI bus masters will release

their REQ signals after having begun a transaction, even if that transaction may require the use of the bus for an

extended time. If the XIO2001 self-parks the bus, then these bus masters will have their transaction lengths

limited to the latency timer setting. This may result in increased arbitration, higher overhead for transactions, and

decreased bus performance.

9.2.1.2.1.2

I/O Characteristics

Figure 27 shows a 3-state bi-directional buffer that represents the I/O cell design for the PCI bus. PCI Bus

Electrical Characteristics , Electrical Characteristics over Recommended Operating Conditions, provides the

electrical characteristics of the PCI bus I/O cell.

NOTE

The PCI bus interface on the bridge meets the ac specifications of the PCI Local Bus

Specification. Additionally, PCI bus terminals (input or I/O) must be held high or low to

prevent them from floating.

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