| 전자부품 데이터시트 검색엔진 |
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L9942 데이터시트(PDF) 17 Page - STMicroelectronics |
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L9942 데이터시트(HTML) 17 Page - STMicroelectronics |
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17 / 37 page ![]() L9942 3 Electrical specifications 17/37 Figure 7. Logic to Set Load Current Limit 3.4.7 PWM Control VS = 7 to 20 V, VCC = 3.0 to 5.3 V, EN=VCC, Tj = -40 to 150 °C, IREF = -200 µA, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. Table 13. PWM Control (see Figure 4 and Figure 7) Symbol Parameter Test Condition Min. Typ. Max. Unit fPWM 1 Frequency of PWM cycles Bit: FRE= 1 20.8 kHz Bit: FRE= 0 31.3 kHz TMD 1 Mixed decay switch off delay time Bits: DM1 DM0= 0 1 4 us Bits: DM1 DM0= 1 0 8 us TFT 1 Glitch filter delay time Bit: FILTER= 0 1.5 us Bit: FILTER= 1 2.5 us Register 0 UP/Down STEP I4 I3 I2 I1 I0 Count by 1,2,4,8 A0 A1 A2 A3 MUX A0 A1 A2 0 0 0 0 1 23 01 2 3 0 1 2 3 Current-Profile Table stored in register2, ...6 A3=0 Adr A[3..0] Phase A Profile 8 Address Calculation I4 I3 I2 I1 I0 Profile 7 I4 I3 I2 I1 I0 Profile 6 I4 I3 I2 I1 I0 Profile 5 I4 I3 I2 I1 I0 Profile 4 I4 I3 I2 I1 I0 Profile 3 I4 I3 I2 I1 I0 Profile 2 I4 I3 I2 I1 I0 Profile 1 I4 I3 I2 I1 I0 Profile 0 5 5 5 5 5 5 5 5 5 A3=1 Adr neg(A[3..0]) A3=0 Adr neg(A[3..0]) Phase B A3=1 Adr A[3..0] Register 1 9 5 DIR P0 P1 P2 P3 P4 PhaseCounter StepMode SR0 SR1 ST1 ST0 Slew Rate DM2 DM1 DM0 MUX MUX I0 I1 I2 I3 I4 I0 I1 I2 I3 I4 DAC Phase B DAC Phase A Decay Mode 5 bit DAC Phase A 5 bit DAC Phase B DC0 DC1 DC2 DAC Scale DAC Full Scale REF REF I MAX I LIMIT B LIMIT A I DI QB1 QB2 QA1 QA2 Qx1LIM I Qx2LIM I QA1LIM I 1000 QB2LIM I 1000 QB1LIM I 1000 QA2LIM I 1000 |
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