SPEAR-09-H022 datasheet(13/55 Pages) STMICROELECTRONICS

부품명	SPEAR-09-H022

상세설명	SPEAr Head ARM 926, 200K customizable eASIC gates, large IP portfolio SoC

PDF	55 Pages

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제조업체	STMICROELECTRONICS [STMicroelectronics]

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13 / 55 page

SPEAR-09-H022

4 Pin Description

13/55

Pin Description

4.1

FUNCTIONAL PIN GROUPS

With reference to

Figure 14. Package schematic - Section 8, here follows the pin list, sorted by

their belonging IP. All supply and ground pins are classified as power signals and gathered in

the

Table 2.

Table 1.

Pin description by functional groups

Group

Signal Name

Ball

Direction

Function

Pin Type

ADC

AIN[0]

V20

Input

ADC analog input channel

Analog buffer,

3.3 V capable

AIN[1]

V19

AIN[2]

V18

AIN[3]

V17

AIN[4]

V16

AIN[5]

V15

AIN[6]

V14

AIN[7]

V12

AIN[8]

V11

AIN[9]

V10

AIN[10]

AIN[11]

AIN[12]

U22

AIN[13]

U21

AIN[14]

U20

AIN[15]

U19

TEST_OUT

V13

Output

ADC output test pad

DEBUG

TEST0

E22

Input

Test configuration port.

For the functional mode they have

to be set to 0

TTL input buffer,

3.3 V capable,

with Pull Down

TEST1

E21

TEST2

D22

TEST3

D21

PLL_BYPASS

Input

Enable / disable PLL bypass

TTL Schmitt trigger

input buffer,

3.3 V capable

eASIC

eASICGP_IO[0]

I/O

eASIC general purpose IO

TTL bidirectional

buffer,

3.3 V capable,

4 mA drive capability

eASICGP_IO[1]

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