R7FA2L1AB2DFM datasheet(36/110 Pages) RENESAS

부품명	R7FA2L1AB2DFM

상세설명	Ultra low power 48 MHz Arm짰 Cortex-M23 core, up to 256-KB code flash memory

PDF	110 Pages

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36 / 110 page

2.3.3

Reset Timing

Table 2.20

Reset timing

Parameter

Symbol

Min

Typ

Max

Unit

Test

conditions

RES pulse width

At power-on

tRESWP

—

Figure 2.7

Not at power-on

tRESW

—

µs

Figure 2.8

Wait time after RES cancellation (at

power-on)

LVD0 enabled*1

tRESWT

—

0.9

—

Figure 2.7

LVD0 disabled*2

—

0.2

—

Wait time after RES cancellation (during

powered-on state)

LVD0 enabled*1

tRESWT2

—

0.9

—

Figure 2.8

LVD0 disabled*2

—

0.2

—

Wait time after internal reset

cancellation (Watchdog timer reset,

SRAM parity error reset, SRAM ECC

error reset, bus master MPU error

reset, bus slave MPU error reset, stack

pointer error reset, software reset)

LVD0 enabled*1

tRESWT3

—

0.9

—

Figure 2.9

LVD0 disabled*2

—

0.15

—

Note 1. When OFS1.LVDAS = 0.

Note 2. When OFS1.LVDAS = 1.

VCC

RES

tRESWP

Internal reset

tRESWT

Figure 2.7

Reset input timing at power-on

RES

Internal reset

tRESWT2

tRESW

Figure 2.8

Reset input timing (1)

RA2L1 Datasheet

2. Electrical Characteristics

R01DS0385EJ0100 Rev.1.00

Aug 06, 2020

Page 36 of 110

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