R5F52105ADFN datasheet(2/223 Pages) RENESAS

2 / 223 page

R01DS0041EJ0150 Rev.1.50

Page 2 of 221

Oct 18, 2013

RX210 Group

1. Overview

1.Overview

1.1

Outline of Specifications

Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different

packages.

Table 1.1 is for products with the greatest number of functions, so numbers of peripheral modules and channels will

differ in accord with the package. For details, see Table 1.2, Comparison of Functions for Different Packages.

This product includes chip version A (part no.: R5F5210xAxxx), chip version B (part no.: R5F5210xBxxx), and chip

version C (part no: R5F5210xCxxx).

For the specification differences between chip versions A, B, and C, see Table 1, Specification Differences

Depending on Chip Versions.

Table 1.1

Outline of Specifications (1 / 5)

Classification

Module/Function

Description

CPU

 Maximum operating frequency: 50 MHz

 32-bit RX CPU

 Minimum instruction execution time: One instruction per state (cycle of the system clock)

 Address space: 4-Gbyte linear

 Register

General purpose: Sixteen 32-bit registers

Control: Eight 32-bit registers

Accumulator: One 64-bit register

 Basic instructions: 73

 DSP instructions: 9

 Addressing modes: 10

 Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

 On-chip 32-bit multiplier: 32  32  64 bits

 On-chip divider: 32 / 32  32 bits

 Barrel shifter: 32 bits

Memory

ROM

 Capacity: 64 K/96 K/128 K/256 K/384 K/512 K/768 Kbytes/1 Mbyte

 50 MHz, no-wait memory access

 On-board programming: 3 types

Off-board programming

RAM

 Capacity: 12 K/16 K/20 K/32 K/64 K/96 Kbytes

 50 MHz, no-wait memory access

E2 DataFlash

 Capacity: 8 Kbytes

 Number of times for programming/erasing: 100,000

MCU operating mode

Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled expansion mode

(software switching)

Clock

Clock generation circuit

 Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,

PLL frequency synthesizer, and IWDT-dedicated on-chip oscillator

 Oscillation stop detection

 Measuring circuit for accuracy of clock frequency (clock-accuracy check: CAC)

 Independent settings for the system clock (ICLK), peripheral module clock (PCLK), external bus clock

(BCLK), and FlashIF clock (FCLK)

The CPU and system sections such as other bus masters run in synchronization with the system

clock (ICLK): 50 MHz (at max.)

Peripheral modules run in synchronization with the peripheral module clock (PCLK): 32 MHz (at

max.)

Devices connected to the external bus run in synchronization with the external bus clock (BCLK):

12.5 MHz (at max.)

The flash peripheral circuit runs in synchronization with the FlashIF clock (FCLK): 32 MHz (at max.)

Reset

RES# pin reset, power-on reset, voltage monitoring reset, watchdog timer reset, independent watchdog

timer reset, deep software standby reset, and software reset

Voltage detection

Voltage detection circuit

(LVDAa)

 When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt

is generated.

Voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels

Voltage detection circuit 1 is capable of selecting the detection voltage from 16 levels

Voltage detection circuit 2 is capable of selecting the detection voltage from 16 levels

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