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TLE7276-2D 데이터시트(PDF) 4 Page - Infineon Technologies AG |
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TLE7276-2D 데이터시트(HTML) 4 Page - Infineon Technologies AG |
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4 / 19 page ![]() TLE7276-2 Pin Configuration Data Sheet 4 Rev. 1.0, 2009-06-01 3 Pin Configuration 3.1 Pin Assignment PG-SSOP-14 Exposed Pad Figure 2 Pin Configuration (top view) 3.2 Pin Definitions and Functions PG-SSOP-14 Exposed Pad Pin No. Symbol Function 1,2,3,5,7 n.c. non connected can be open or connected to GND 4GND Ground 6EN Enable Input high level input signal enables the IC; low level input signal disables the IC; integrated pull-down resistor 8,10,11,12,14 n.c. non connected can be open or connected to GND 9Q Output block to ground with a capacitor close to the IC terminals, respecting the values given for its capacitance and ESR in “Functional Range” on Page 6 13 I Input block to ground directly at the IC with a ceramic capacitor Pad – Exposed Pad connect to GND and heatsink area |
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