A6986H3V3 datasheet(45/71 Pages) STMICROELECTRONICS

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Figure 44. Voltage supervisor operation during OVP

7.5

Synchronization (LNM)

The synchronization feature helps the hardware designer to prevent beating frequency noise that is an issue

when multiple switching regulators populate the same application board.

7.5.1

Embedded master - slave synchronization

The A6986H synchronization circuitry features the same switching frequency for a set of regulators simply

connecting their SYNCH pin together, so preventing beating noise. The master device provides the

synchronization signal to the others since the SYNCH pin is I/O able to deliver or recognize a frequency signal.

For proper synchronization of multiple regulators, all of them have to be configured with the same switching

frequency (see Table 6. fSW selection TJ = - 40 to 135 °C, VIN= 12 V unless otherwise specified.), so the same

resistor connected at the FSW pin.

In order to minimize the RMS current flowing through the input filter, the A6986H device provides a phase shift of

180° between the master and the SLAVES. If more than two devices are synchronized, all slaves will have a

common 180° phase shift with respect to the master.

Considering two synchronized A6986H which regulate the same output voltage (i.e.: operating with the same duty

cycle), the input filter RMS current is optimized and is calculated as:

IRMS= IOUT2⋅ 2D⋅(1−2D)

ifD<0.5

IOUT2⋅ (2D−1)⋅(2−2D) ifD>0.5

(42)

The graphical representation of the input RMS current of the input filter in the case of two devices with 0° phase

shift (synchronized to an external signal) or 180° phase shift (synchronized connecting their SYNCH pins)

regulating the same output voltage is provided in the figure below. To dimension the proper input capacitor please

refer to Section 7.6.1 Input capacitor selection).

A6986H

Synchronization (LNM)

DS12861 - Rev 3

page 45/71

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