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L5050STR 데이터시트(PDF) 11 Page - STMicroelectronics |
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L5050STR 데이터시트(HTML) 11 Page - STMicroelectronics |
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11 / 20 page ![]() DS12548 Rev 3 11/20 L5050S Protection features 19 3 Protection features 3.1 Voltage regulator Voltage regulator uses a p-channel MOS transistor as a regulating element. With that structure, a very low dropout voltage at current up to 50mA is obtained. The output voltage is regulated up to transient input supply voltage of 40 V. The high-precision of the output voltages (±2%) is obtained with a pre-trimmed reference voltage. The voltage regulator automatically adapts its own quiescent current to the output current level. In light load conditions, the quiescent current goes down to 50 µA only in low consumption mode. This procedure features a certain hysteresis on the output current (see Figure 8). Short-circuit protection to GND and a thermal shutdown are provided. Figure 18. Application schematic – L5050S The input capacitor C1 is necessary as backup supply for short battery voltage interruption which may occur on the line. Its value should be chosen according to the relevant application requirement. The second input capacitor C2 ≥ 220 nF is needed when the C1 is too distant from the VS pin and it compensates smooth line disturbances. The C0 ceramic capacitor, connected to the output pin, is for bypassing to GND the high-frequency noise and it guarantees stability even during sudden line and load variations. Suggested value is C0 = 220 nF with ESR ≥ 100 mΩ. Stability region is reported in Figure 19. Figure 19. Stability region L5050S C2 VS1 En1 GND1 C0 VO1 VBAT C1 0.01 0.1 1 10 0.22 0.47 1 2.2 3.3 4.7 10 Co (µF) ESR min STABILITY REGION UNTESTED REGION |
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