| 전자부품 데이터시트 검색엔진 |
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L7983PUR 데이터시트(PDF) 4 Page - STMicroelectronics |
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L7983PUR 데이터시트(HTML) 4 Page - STMicroelectronics |
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4 / 43 page ![]() 2 Pin settings Figure 3. Pin connection (top view) 1 VOUT/FB 2 3 4 5 EXPOSED PAD TO GND 10 9 8 7 6 VBIAS VCC FSW LNM/LCM GND LX VIN EN/UVLO RST Table 1. Pin description N° Pin Description 1 VOUT/FB Output voltage sensing. This pin operates as VOUT or FB accordingly with selected part number: • VOUT is output voltage sensing with selected internal voltage divider. • FB is output voltage sensing with external resistor divider. 2 VBIAS Input supply of the integrated LDO. Typically connected to the regulated output voltage or an auxiliary rail to increase the efficiency at light load. Connect to GND if not used or bypass with a 100 nF ceramic capacitor if supplied by the output voltage or by an auxiliary rail. 3 VCC Output of the integrated LDO that supplies the embedded analog circuitry. Connect a ceramic capacitor (470 nF typ.) to filter internal voltage reference. 4 FSW Switching frequency programming pin. Connect an external resistor to VCC or GND. 5 LNM/LCM Dynamic pin selection between Low Consumption Mode (LCM, active low) and Low Noise Mode operation (LNM, active high). This pin can also be used for synchronization with an external clock (clock-in function). 6 RST Active low open collector output for output monitoring and power-up reset sequencing. RST is driven in low impedance when the output voltage is out of regulation and released once the output voltage becomes valid. 7 EN/UVLO Active high enable pin, VIN compatible. It can be exploited with an external resistor divider to adjust the input undervoltage lockout (UVLO). 8 VIN DC input voltage 9 LX Switching node 10 GND Ground -- E.P. Exposed pad must be connected to GND L7983 Pin settings DS13354 - Rev 1 page 4/43 |
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