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Design overview

The architecture is based on three main stages: the power supply stage implementing a QR fly-back topology

based on the STD7N65M6 MDmesh™ M6 primary MOSFET, the power control stage embedding the STCH03

primary side PWM controller, and the digital control stage based on the STM32G071KB Arm Cortex-M0+ MCU

The USB-PD 3.0 Middleware stack,coming from the STM32CubeG0 package, runs over the STM32G071KBU6N.

On the primary side, the STCH03 controller combines a high performance low-voltage PWM controller chip with a

650 V HV start-up cell in the same package, ensuring low pin count. It can operate in different modes, QR active

mode, valley skipping mode and burst mode, to guarantee high efficiency at different input voltage and output

load conditions.

On the secondary side, the STM32G0 provides additional integration value, thanks to the embedded UCPD

interface which manages the USB Type-C connector and the Power Delivery 3.0 communication protocol, while

controlling the adaptive synchronous rectification through its versatile peripherals and feature set.

The companion TCPP01-M2 safely interfaces the USB-C connector to the MCU, ensuring the highest robustness

and protecting against any destructive electrostatic discharge (ESD). It features 22 V tolerant ESD protection as

per IEC61000-4-2 level 4 on USB type-C connector configuration channel (CC) pins. The ESDA15P60 ensures

STEVAL-USBPD27S

Design overview

DB4227 - Rev 2

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