ZMOD4450 Datasheet

© 2019 Integrated Device Technology, Inc.

13

October 30, 2019

Figure 6. Bus Timing

Table 9.

Bus Timing Characteristics

Parameter

Symbol

Standard Mode

Fast Mode

Units

Maximum SCL clock frequency

100

400

kHz

Minimum START condition hold time relative to SCL edge

4

µs

Minimum SCL clock LOW width

4.7

µs

Minimum SCL clock HIGH width

4

µs

Minimum START condition setup time relative to SCL edge

4.7

µs

Minimum data hold time on SDA relative to SCL edge

0

µs

Minimum data setup time on SDA relative to SCL edge

0.1

0.1

µs

Minimum STOP condition setup time on SCL

4

µs

Minimum bus free time between stop condition and start condition

4.7

µs

SDA

SCL