전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

GS9021 데이터시트(PDF) 3 Page - Gennum Corporation

부품명 GS9021
상세설명  EDH Coprocessor
PDF  26 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  GENNUM [Gennum Corporation]
홈페이지  http://www.gennum.com
Logo GENNUM - Gennum Corporation

GS9021 데이터시트(HTML) 3 Page - Gennum Corporation

  GS9021 Datasheet HTML 1Page - Gennum Corporation GS9021 Datasheet HTML 2Page - Gennum Corporation GS9021 Datasheet HTML 3Page - Gennum Corporation GS9021 Datasheet HTML 4Page - Gennum Corporation GS9021 Datasheet HTML 5Page - Gennum Corporation GS9021 Datasheet HTML 6Page - Gennum Corporation GS9021 Datasheet HTML 7Page - Gennum Corporation GS9021 Datasheet HTML 8Page - Gennum Corporation GS9021 Datasheet HTML 9Page - Gennum Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 3 / 26 page
background image
521 - 65 - 05
3
AC ELECTRICAL CHARACTERISTICS
VDD = 5.0V, TA = 0 to 70°C unless otherwise shown.
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
NOTES
Input Clock Frequency
-
-
54
MHz
Clock Pulse Width Low
tPWL
7.4
-
-
ns
Clock Pulse Width High
tPWH
7.4
-
-
ns
Input Setup Time
tS
3-
-
ns
1, 2
Input Hold Time
tH
3-
-
ns
1, 2
Output Delay Time
tOD
with 10pF loading
-
-
15
ns
2
Output Hold Time
tOH
with 10pF loading
5
-
-
ns
2
Output Setup Time
tOS
with 10pF loading
3.5
-
-
ns
2,4
Flag Port Disable Time
tFDIS
with 25pF loading
-
-
15
ns
Flag Port Enable Time
tFEN
with 25pF loading
-
-
16
ns
I²C Clock Frequency
ƒSCL
-
-
400
kHz
Host Interface Setup Time
tHS
6-
-
ns
Host Interface Hold Time
tHH
6-
-
ns
Host Interface Output
Enable Time
tHEN
with 25pF loading
-
-
21
ns
Host Interface Output
Disable Time
tHDIS
with 25pF loading
-
-
10
ns
Reset Time Pulse Width
tRESET
100
-
-
ns
Device Latency
tLAT
888
clks
3
NOTES
1. See section 1.2 for a list of signals synchronous and asynchronous to PCLKIN.
2. See Figures 1 and 2.
3. Latency is defined as the number of clock cycles between the time when the data is latched into the device and when the
corresponding output data is clocked into the next device as shown in Figure 3.
4) Based upon 54MHz clock (18.5ns). Output Setup Time = Clock Period - Output Delay Time



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com