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TMP139AIYAHR 데이터시트(PDF) 40 Page - Texas Instruments

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부품명 TMP139AIYAHR
상세설명  TMP139 0.5 째C Accuracy, JEDEC DDR5 Grade B, Digital Temperature Sensor With I2C and I3C Interface
PDF  58 Pages
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홈페이지  http://www.ti.com
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7.6.10 MR26: TS Configuration (address = 1Ah) [reset = 00h]
The MR26 register may be used by the host to disable the temperature sensor. The device will stop temperature
conversion or, if there is an ongoing conversion when the bit is set, then it shall complete the current conversion
and then disable the temperature sensor.
Return to Register Map.
Figure 7-56. MR26: Temperature Sensor Configuration Register
7
6
5
4
3
2
1
0
Reserved
DIS_TS
R-00h
RW-0
Table 7-22. MR26: Temperature Sensor Configuration Field Descriptions
Bit
Field
Type
Reset
Description
7:1
Reserved
R
00h
Reserved
0
DIS_TS
RW
0
Disable temperature sensor
0 = Enable temperature sensor.
1 = Disable temperature sensor.
7.6.11 MR27: Interrupt Configuration (address = 1Bh) [reset = 00h]
Return to Register Map.
Figure 7-57. MR27: Interrupt Configuration Register
7
6
5
4
3
2
1
0
CLR_GLOBAL
Reserved
IBI_ERROR_EN IBI_TS_CRIT_
LOW_EN
IBI_TS_CRIT_
HIGH_EN
IBI_TS_LOW_E
N
IBI_TS_HIGH_E
N
W1C
R-00
R-0
RW-0
RW-0
RW-0
RW-0
Table 7-23. MR27: Interrupt Configuration Field Descriptions
Bit
Field
Type
Reset
Description
7
CLR_GLOBAL
R0-W1C 0
Global clear event status and In Band Interrupt (IBI) status
1 = Write '1' to clear the registers MR48, MR51 and MR52.
Writing a '0' has no effect on registers MR48, MR51 and MR52.
6:5
Reserved
R
00
Reserved
4
IBI_ERROR_EN
R
0
In band interrupt (IBI) enable for MR52 error log.1
0 = Disable. Errors logged in MR52 register bits do not generate
an IBI to host.
1 = Enable. Errors logged in MR52 register bits generate an IBI
to host.
3
IBI_TS_CRIT_LOW_EN
RW
0
In band interrupt (IBI) enable for temperature sensor critical low.
0 = Disable. MR51 register TS_CRIT_LOW_STATUS bit does
not generate an IBI to host.
1 = Enable. MR51 register TS_CRIT_LOW_STATUS bit
generates an IBI to host.
2
IBI_TS_CRIT_HIGH_EN
RW
0
In band interrupt (IBI) enable for temperature sensor critical
high.
0 = Disable. MR51 register TS_CRIT_HIGH_STATUS bit does
not generate an IBI to host.
1 = Enable. MR51 register TS_CRIT_HIGH_STATUS bit
generates an IBI to host.
1
IBI_TS_LOW_EN
RW
0
In band interrupt (IBI) enable for temperature sensor low.
0 = Disable. MR51 register TS_LOW_STATUS bit does not
generate an IBI to host.
1 = Enable. MR51 register TS_LOW_STATUS bit generates an
IBI to host.
TMP139
SNIS217 – DECEMBER 2020
www.ti.com
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