 2020 Microchip Technology Inc.

DS20006356A-page 9

DSA400

4.4

LVCMOS

50 Ω

27Ω

FIGURE 4-4:

Typical LVCMOS Termination Scheme.

The 27Ω Series resistor complements the output impedance of about 23Ω to 50Ω impedance to match the line 50Ω

characteristic impedance to prevent reflections from the driver back to the receiver.

TABLE 4-4:

LVCMOS OUTPUTS

Parameter

Symbol

Min.

Typ.

Max.

Units

Condition

Output Logic

Levels

—

—

V

Output Logic High, I = ±6 mA

—

—

Output Logic Low, I = ±6 mA

Output

Transition Time

(Note 1)

—

1.1

2.0

ns

—

1.3

2.0

Frequency

—

—

100

MHz

—

Output Duty

Cycle

SYM

44

—

55

%

—

IO Supply

Current (Note 2)

—

11

14

mA

Period Jitter

—

3

—

Integrated

Phase Noise

—

0.3

—

200 kHz to 20 MHz @ 125 MHz

—

0.38

—

100 kHz to 20 MHz @ 125 MHz

—

1.7

2.0

12 kHz to 20 MHz @125 MHz

Note 1: See the Output Waveform section for more information.