Data Sheet

AD4020/AD4021/AD4022

Rev. B | Page 29 of 39

STATUS BITS

A set of six optional status bits can be appended to the end of

each conversion result. The status bits allow the digital host to

check the state of the input overvoltage protection circuit and

verify that the ADC features are configured correctly without

interrupting conversions. The status bits are enabled when the

status bits enable bit in the configuration register is set to 1 (see

Configuration Register Details section). Table 15 shows a

description of each status bit.

When enabled, the status bits are clocked out MSB first starting

on the SCK falling edge immediately following the LSB of the

conversion result. The SDO line returns to high impedance

after the sixth status bit is clocked out (except in daisy-chain

mode). The user is not required to clock out all status bits to

start the next conversion. For example, if the digital host needs

to monitor the OV clamp flag but also needs to minimize the

SCK frequency, the remaining status bits can be ignored to limit

the number of SCK pulses required per conversion period.

When using multiple AD4020/AD4021/AD4022 devices in

daisy-chain mode, however, all six status bits must be clocked

out for each connected device.

Figure 52 shows the serial interface timing for CS mode, 3-wire

without busy indicator with all six status bits, Bits[5:0] (see

Figure 52), clocked out.

Table 15. Status Bits Descriptions

Bit

Bit Name

Description

5

OV clamp flag

Indicates the state of the OV

clamp flag in the configuration

register.

4

Span compression

Indicates the state of the span

compression enable bit in the

configuration register.

3

High-Z mode

Indicates the state of the High-Z

mode enable bit in the

configuration register.

2

Turbo mode

Indicates the state of the turbo

mode enable bit in the

configuration register.

[1:0]

Reserved

Reserved.

SDO

D19

D18

D17

D1

D0

SCK

12

3

18

19

20

CNV

CONVERSION

ACQUISITION

ACQUISITION

SDI = 1

25

26

STATUS BITS B[5:0]

B1

B0

24

Figure 52. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram Including Status Bits