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MX55 데이터시트(PDF) 3 Page - Microchip Technology

부품명 MX55
상세설명  Low Jitter Crystal Oscillator
PDF  28 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MX55 데이터시트(HTML) 3 Page - Microchip Technology

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 2018 Microchip Technology Inc.
DS20005972A-page 3
MX55/57
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Input Voltage, (VIN) ............................................................................................................................–0.3V to VDD +0.3V
Supply Voltage ......................................................................................................................................... –0.3V to + 4.0V
ESD Protection (HBM) ............................................................................................................................................... 2 kV
ESD Protection (MM) ................................................................................................................................................200V
ESD Protection (CDM) ............................................................................................................................................ 1.5 kV
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended
periods may affect device reliability.
TABLE 1-1:
ELECTRICAL CHARACTERISTICS
Electrical Characteristics: VDD = 2.375V to 3.63V, TA = –40°C to +85°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Supply Voltage
(Note 1)
VDD
2.375
—
3.63
V
—
Supply Current
IDD
—85
95
mA
Output enabled LVCMOS (no load).
—
105
120
LVPECL
—80
90
LVDS
—
85
95
HCSL
—
68
—
Output disabled (Tri-state)
Frequency
Stability
Δf
—
—
±50
ppm
Inclusive of initial accuracy, temperature
drift, aging, shock and vibration.
Start-up Time
tSU
——
20
ms
From 90% VDD to valid clock output,
T = +25°C
Input Logic
Levels
VIH
2—
VDD+0.3
V
Input logic-high
VIL
–0.3
—
0.8
Input logic-low
Enable Active
High Option
(Note 2)
—
—
50
—
kΩ
Pull-up resistor on Pin 1 or 2
Enable Active
Low Option
(Note 3)
—
—
50
—
kΩ
Pull-down resistor on Pin 1 or 2
LVCMOS
Frequency
f0
2.5
—
250
MHz
—
Integrated Phase
Noise (Random)
ϕj
—131
—
fsRMS
12 kHz to 5 MHz @ 25 MHz
—
77
—
1.875 MHz to 5 MHz @ 25 MHz
Output High
Voltage
VOH
VDD–0.8
—
—
V
RL = 50Ω termination from Q to VDD–2
Output Low
Voltage
VOL
——
0.6
V
Output Rise/Fall
Time
Tr/Tf
100
—
500
ps
—
Duty Cycle
SYM
45
—
55
%
—
LVPECL
Frequency
f0
2.5
—
850
MHz
—
Integrated Phase
Noise (Random)
ϕj
—130
—
fsRMS
12 kHz to 20 MHz @ 200 MHz
—
96
—
1.875 MHz to 20 MHz @ 200 MHz



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