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OPA607 데이터시트(PDF) 30 Page - Texas Instruments

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부품명 OPA607
상세설명  OPAx607 50-MHz, Low-Power, Rail-to-Rail Output CMOS Operational Amplifier for Cost Sensitive Systems
PDF  45 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power-supply pins of the circuit as a whole and of the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance
power sources local to the analog circuitry.
– Connect low-equivalent series resistance (ESR), 0.1-µF ceramic bypass capacitors between each supply
pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is
applicable for single-supply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Make
sure to physically separate digital and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much better than
crossing in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance; see Figure 11-1 and Figure 11-2.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
11.2 Layout Examples
V-
OUTPUT
GND
GND
GND
Figure 11-1. Operational Amplifier Board Layout
for a Noninverting Configuration
+
±
V+
INPUT
V-
C3
C4
R2
C1
R1
C2
OUTPUT
U1
OPAx607
1
2
3
4
R3
6
5
Figure 11-2. Layout Example Schematic
OPA607, OPA2607
SBOS981I – OCTOBER 2019 – REVISED FEBRUARY 2021
www.ti.com
30
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA607 OPA2607



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