VD6640 datasheet(27/126 Pages) STMICROELECTRONICS

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DocID023597 Rev 11

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VG6640, VD6640

Control interface

125

Control interface

Control and status data is transferred to and from the image sensor using the control

interface. The internal registers in the image sensor can be configured or read back by a

companion device containing an I2C master (SDA, SCL). Commands are in the format

specified by the control interface in the MIPI CSI-2 specification (16-bit index followed by 8-

bit data).

The control interface is an I2C-type interface with two signals: serial data line (SDA) and

serial clock line (SCL). Each device connected to the bus uses a unique address and a

simple master/slave relationships exists.

Note:

Technically, the control interface serial bus is a protocol and subset of the I2C standard. For

brevity, this datasheet will refer to the control interface as I2C.

By default the image sensor operates in I2C Fast mode (up to 400kHz). For operation in

Fast+ mode (up to 1MHz), this must be enabled by setting the relevant register.

Note:

Operation in Fast+ mode requires a change in value of pull-up resistor to ensure fast

enough rise time of the signals (see Section 11.5: I2C pull-up resistors).

Both SDA and SCL lines are connected to a positive supply voltage using pull-up resistors

located externally or on the companion device. Lines are only actively driven low. A high

condition occurs when lines are floating and the pull-up resistors pull lines up. When no data

is transmitted both lines are high. SeeChapter 9: Electrical characteristics on page 87 for

electrical and timing information.

Clock signal (SCL) generation is performed by the master device. The master device

initiates data transfer. The I2C bus on the image sensor uses a default device address of

0x20. This slave address is held in register 0x41A8 as detailed in the register map.

Figure 9. Data transfer protocol

Information is packed in 8-bit packets (bytes) always followed by an acknowledge bit, Ac for

camera acknowledge and Am for master acknowledge. The internal data is produced by

sampling SDA at a rising edge of SCL. The external data must be stable during the high

period of SCL. The exceptions to this are start (S) or stop (P) conditions when SDA falls or

rises respectively, while SCL is high.

A message contains a series of bytes preceded by a start condition and followed by either a

stop or repeated start (another start condition but without a preceding stop condition)

followed by another message. The first byte contains the device address (0x20 by default)

and also specifies the data direction. If the least significant bit (lsb) is low (that is, 0x20) the

Ac/Am

Start condition

Stop condition

SDA

SCL

Acknowledge

Address or data byte

MSB

LSB

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