VSC8221HH datasheet(68/138 Pages) MICROSEMI

68 / 138 page

VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

68 of 106

106

0.12 – Auto-Negotiation Enable

After a power-up or reset, the PHY automatically activates the auto-negotiation state machine, setting bit 0.12 to a “1”. if a “0” is

written to bit 0.12, the auto-negotiation process is disabled and the present contents of the PHY’s SMi register bits determine

the operating characteristics. Note that auto-negotiation is always required in 1000BASE-T mode.

0.11 – Power-Down

Power-Down functions the same as Software Reset, except that it is not self-clearing, and that R/W SMi bits are not restored to

their default states by Power-Down. The RGMii pins (except for SMi pins MDC, MDiO, and MDiNT#) are electrically isolated

during power-down. After Power-Down is released (i.e., set to “0”), the PHY will be ready for normal operation before the next

SMi transaction. if auto-negotiation is enabled, the PHY will begin auto-negotiation immediately upon exiting Power-Down.

0.10 – isolate1

When isolate is asserted (i.e., set to “1”), all Serial MAC outputs (except for MDiO) will be high impedance. Operation of the

PHY is otherwise unaffected. For example, if isolate is asserted while CAT5 auto-negotiation is under way, auto-negotiation will

continue unaffected.

0.9 – Restart Auto-Negotiation

When restart auto-negotiation is asserted (i.e., set to “1”), the auto-negotiation state machine will restart the auto-negotiation

process, even if it is in the midst of an auto-negotiation process. This control bit is self-clearing, meaning that it will always return

a “0” when read.

0.8 – Duplex Mode

Bit 0.8 determines the duplex mode of the VSC8221 when auto-negotiation is disabled. Changes to the state of Duplex Mode

while auto-negotiation is enabled are ignored.

0.7 – Reserved

0.5:0 – Reserved

1When set, while the PHY’s SerDes side auto-negotiation function is enabled, the PHY will drop the CAT5 link. Also, setting of this bit does not

disable the output clock on the SCLKP and SCLKN pins.

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