AD9361BBCZ-CSL datasheet(20/33 Pages) AD

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AD9361S-CSL

Commercial Space Product

Rev. 0 | Page 20 of 33

Pin No.

Type1

Mnemonic

Description

K10

I/O

P1_D2/RX_D1_N

Digital Data Port P1/Receive Differential Output Bus. This is a dual

function pin. As P1_D2, it functions as part of the 12-bit bidirectional

parallel CMOS level Data Port 1. Alternatively, as RX_D1_N, this pin

can function as part of the LVDS 6-bit RX differential output bus with

internal LVDS termination.

K11

I/O

P1_D0/RX_D0_N

Digital Data Port P1/Receive Differential Output Bus. This is a dual

function pin. As P1_D0, it functions as part of the 12-bit bidirectional

parallel CMOS level Data Port 1. Alternatively, as RX_D0_N, this pin

can function as part of the LVDS 6-bit RX differential output bus with

internal LVDS termination.

RBIAS

Bias Input Reference. Connect this pin through a 14.3 kΩ

(1% tolerance) resistor to ground.

AUXADC

Auxiliary ADC Input. If this pin is unused, tie it to ground.

SPI_DO

SPI Serial Data Output in 4-Wire Mode, or High-Z in 3-Wire Mode.

M1, M2

RX1A_P, RX1A_N

Receive Channel 1 Differential Input A. Alternatively, each pin can be

used as a single-ended input. Tie unused pins to ground.

TX_MON1

Transmit Channel 1 Power Monitor Input. When this pin is unused, tie it

to ground.

M7, M8

TX1A_P, TX1A_N

Transmit Channel 1 Differential Output A. Tie unused pins to 1.3 V.

M9, M10

TX1B_P, TX1B_N

Transmit Channel 1 Differential Output B. Tie unused pins to 1.3 V.

M11, M12

XTALP, XTALN

Reference Frequency Crystal Connections. When a crystal is used,

connect it between these two pins. When an external clock source is

used, connect it to XTALN and leave XTALP unconnected.

I is input, O is output, I/O is input/output, and DNC is do not connect.

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