ADS9-V2EBZ datasheet(14/133 Pages) AD

14 / 133 page

ADRV9029

Data Sheet

Rev. 0 | Page 14 of 133

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Spot Phase Noise

PLL bandwidth optimized to minimize

phase noise at offsets >200 kHz

100 kHz Offset

−91

dBc/Hz

1 MHz Offset

−120

dBc/Hz

10 MHz Offset

−143

dBc/Hz

REFERENCE CLOCK

(DEV_CLK± INPUT SIGNAL)

DEV_CLK+,

DEV_CLK−

Frequency Range

1000

MHz

Signal Level (Differential)

0.2

1.0

V p-p

AC-coupled, common-mode voltage

internally supplied; for optimal spurious

performance and to meet the specified PLL

performance parameters, use a 1 V p-p input

clock

SYSTEM REFERENCE INPUTS

SYSREF+,

SYSREF−

Logic Compliance

LVDS/LVPECL

Differential Input Voltage

400

800

1800

mV p-p

External 100 Ω differential termination

Input Common-Mode

Voltage

0.675

2.0

Input Resistance (Differential)

kΩ

Input Capacitance

(Differential)

AUXILIARY CONVERTERS

ADC

Resolution

Bits

Input Voltage

Minimum

0.05

Maximum

0.95

AUXDAC_0

Resolution

Bits

Output Voltage

Minimum

0.2

Maximum

VDDA_1P8 − 0.25

AUXDAC_1 To AUXDAC_7

Resolution

Bits

Output Voltage

Minimum

0.1

Maximum

VDDA_1P8 − 0.1

Drive Capability

DIGITAL SPECIFICATIONS

Table 3.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIGITAL SPECIFICATIONS—

SINGLE-ENDED SIGNALS

Applies to the following pins:

GPIO_x, GPINTx, TXx_EN,

RXx_EN, ORX_CTRL_x, TEST_EN,

RESET, SPI_EN, SPI_CLK, SPI_DO,

and SPI_DIO

Logic Inputs

Input Voltage

High Level

VIF × 0.65

VIF + 0.18

Low Level

−0.30

VIF × 0.35

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