M41T50 datasheet(9/23 Pages) STMICROELECTRONICS

9 / 23 page

9/23

M41T50

Figure 8. READ Mode Sequence

Figure 9. Alternative READ Mode Sequence

WRITE Mode

In this mode the master transmitter transmits to

the M41T50 slave receiver. Bus protocol is shown

in Figure 10., page 10. Following the START con-

dition and slave address, a logic '0' (R/W=0) is

placed on the bus and indicates to the addressed

device that word address “An” will follow and is to

be written to the on-chip address pointer. The data

word to be written to the memory is strobed in next

and the internal address pointer is incremented to

the next address location on the reception of an

acknowledge clock. The M41T50 slave receiver

will send an acknowledge clock to the master

transmitter after it has received the slave address

see Figure 7., page 8 and again after it has re-

ceived the word address and each data byte.

AI00899

BUS ACTIVITY:

SDA LINE

BUS ACTIVITY:

MASTER

DATA n

DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

SLAVE

ADDRESS

AI00895

BUS ACTIVITY:

SDA LINE

BUS ACTIVITY:

MASTER

DATA n

DATA n+1

DATA n+X

SLAVE

ADDRESS

M41T50 데이터시트(PDF) 9 Page - STMicroelectronics

M41T50 데이터시트(HTML) 9 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

데이터시트 다운로드

링크 URL