I

The following specifications apply for V

Symbol

Parameter

Conditions

LM4846

Units

(Limits)

Typical

(Note 4)

Limits

(Notes 5,

10)

t

1

I

2.5

µs (max)

t

2

I

100

ns (min)

t

3

I

100

ns (min)

t

4

Start Condition Time

100

ns (min)

t

5

Stop Condition Time

100

ns (min)

f

SPI

Maximum SPI Frequency

1000

kHz (max)

t

EL

SPI ENB Low Time

100

ns (min)

t

DS

SPI Data Setup Time

100

µs (max)

t

ES

SPI ENB Setup Time

100

ns (min)

t

DH

SPI Data Hold Time

100

ns (min)

t

EH

SPI Enable Hold Time

100

ns (min)

t

CL

SPI Clock Low Time

500

ns (min)

t

CH

SPI Clock High Time

500

ns (min)

t

CS

SPI Clock Transition Time

100

ns (min)

V

IH

I

0.7xI

V

DD

V (min)

V

IL

I

0.3xI

V

DD

V (max)

Note 1: See AN-450 "Surface Mounting and their effects on Product Reliability" for other methods of soldering surface mount devices.

Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and

test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

Note 3: Human body model, 100pF discharged through a 1.5k

Ω resistor.

Note 4: Typical specifications are specified at +25˚C and represent the most likely parametric norm.

Note 5: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 6: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200pF cap is charged to the specified voltage, then discharged directly into the

IC with no external series resistor (resistance of discharge path must be under 50

Ω).

Note 7: All voltages are measured with respect to the ground pin, unless otherwise specified.

Note 8: The given

Note 9: Datasheet min/max specifications are guaranteed by design, test, or statistical analysis.

Note 10: Potentially worse case: All three input stages are DC coupled to the BTL output stage.

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