ADSP21569WCBCZ10RL datasheet(76/104 Pages) AD

76 / 104 page

Rev. B

Page 76 of 104

February 2021

ADSP-21562/21563/21565/21566/21567/21569

Precision Clock Generator (PCG) (Direct Pin Routing)

This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes inputs directly from the DAI

pins (via pin buffers) and sends outputs directly to the DAI pins. For the other cases, where the PCG inputs and outputs are not directly

routed to/from DAI pins (via pin buffers), there is no timing data available. All timing parameters and switching characteristics apply to

external DAI pins (DAI0_PINx).

Table 50. PCG (Direct Pin Routing)

Parameter

Min

Max

Unit

Timing Requirements

tPCGIP

Input Clock Period

tSCLK0 × 2

tSTRIG

PCG Trigger Setup Before Falling Edge of PCG Input

Clock

4.5

tHTRIG

PCG Trigger Hold After Falling Edge of PCG Input

Clock

3ns

Switching Characteristics

tDPCGIO

PCG Output Clock and Frame Sync Active Edge Delay

After PCG Input Clock

210

tDTRIGCLK

PCG Output Clock Delay After PCG Trigger

2 + (2.5 × tPCGIP)

13.5 + (2.5 × tPCGIP)ns

tDTRIGFS

1 D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2156x SHARC+ Processor Hardware Reference.

PCG Frame Sync Delay After PCG Trigger

2.5 + ((2.5 + D – PH) × tPCGIP)

13.5 + ((2.5 + D – PH) × tPCGIP)ns

tPCGOW

2 Normal mode of operation.

Output Clock Period

2 × tPCGIP – 1

Figure 29. PCG (Direct Pin Routing)

DAI0_PIN20–1

PCG_TRIGx_I

DAI0_PIN20–1

PCG_EXTx_I

(CLKIN)

DAI0_PIN20–1

PCG_CLKx_O

DAI0_PIN20–1

PCG_FSx_O

tDTRIGFS

tDTRIGCLK

tDPCGIO

tSTRIG

tHTRIG

tPCGOW

tDPCGIO

tPCGIP

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