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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HT83072 데이터시트(PDF) 17 Page - Holtek Semiconductor Inc |
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HT83072 데이터시트(HTML) 17 Page - Holtek Semiconductor Inc |
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17 / 21 page  HT83XXX Rev. 0.10 17 August 25, 2003 Preliminary Input/Output Ports There are 8 bidirectional input/output lines in the microcontroller, labeled from PA, which are mapped to the data memory of [12H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction ²MOV A, [m]² (m=12H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC) to con- trol the input/output configuration. With this control reg- ister, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an in- put, the corresponding latch of the control register must write ²1². The input source also depends on the control register. If the control register bit is ²1², the input will read the pad state. If the control register bit is ²0², the contents of the latches will move to the internal bus. The latter is possible in the ²read-modify-write² instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H. After a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high options). Each bit of these input/output latches can be set or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H) instruc- tions. Some instructions first input data and then follow the output operations. For example, ²SET [m].i², ²CLR [m].i ², ²CPL [m]², ²CPLA [m]² read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. The wake-up capability of port A is determined by mask option. There is a pull-high option available for all I/O lines. Once the pull-high option is selected, all I/O lines have pull-high resistors. Otherwise, the pull-high resistors are absent. It should be noted that a non-pull-high I/O line operating in input mode will cause a floating state. Q D C K S Q Q D C K S Q M U X D a t a B u s W r i t e C o n t r o l R e g i s t e r C h i p R e s e t R e a d C o n t r o l R e g i s t e r W r i t e I / O R e a d I / O S y s t e m W a k e - U p ( P A o n l y ) W e a k P u l l - u p P A 0 ~ P A 7 M a s k O p t i o n M a s k O p t i o n V D D V D D Input/Output Ports |
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