ATXP5 V1.0
Jumper Free Over Clock Controller
5
Technology Corporation
5. Configuration Registers
Register
Offset Power on/Reset
Default value
Description
CPU FID Output
Control Register
02h
00000000b
<7:5> Reserved.
<4> CPU/CS FID Output Enable
= 0
FIDIN pins pass to FIDCS and FIDCPU pins.
= 1
FIDCS pins are controlled by CR03 bit
3~0(CS FID) and FIDCPU pins are controlled
by CR02 bit 3~0(CPU FID).
<3:0> CPU FID output value.
This register is reset by 3VSB, RSTOUT#, and New
CPU events.
Chipset FID
Output Data
Register
03h
00000000b
<7:4> Reserved.
<3:0> CS FID Output Value.
This register is reset by VBAT.
NEW CPU
Status/Control /
GPIO4-0 Input
Enable Register
05h
00000000b
<7> New CPU Status
<6> Clear New CPU Status.
<5:0> Reserved.
Watching-Dog
Timer Register
07h
00000000b
Watching-Dog Timer Register
<7:0> Read this register means how much time left
that Watching-Dog Timer will be time-out.
Write this register to set a time into
Watching-Dog Timer.
Watching-Dog
Timer
Status/MISC
Control Register
08h
00000000b
<7> Watching-Dog Timer time-out status
Register
= 0 No Watching-Dog time-out event.
= 1 Watching-Dog time-out event
exists.
Write “0” clear this status
<6> Watching-Dog Timer Enable
<5:4> Reserved.
<3:2> Watching-Dog Timer time-unit select
= 00 1 second.
= 01 0.1 second.
= 10 10 mini-second.
= 11 1 mini-second.
<1:0> RSTOUT# pulse width select
= 00 1 second.
= 01 0.1 second.
= 10 10 mini-second.
= 11 1 mini-second.
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