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DAC8581IPWR 데이터시트(PDF) 3 Page - Texas Instruments |
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DAC8581IPWR 데이터시트(HTML) 3 Page - Texas Instruments |
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3 / 14 page ![]() www.ti.com ELECTRICAL CHARACTERISTICS DAC8581 SLAS481A – AUGUST 2005 – REVISED AUGUST 2005 All specifications at T A = TMIN to TMAX, +AVDD = +5 V, –AVDD = –5 V, DVDD = +5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE Resolution 16 Bits Linearity error VREF = 4.096 V ±0.03 ±0.1 %FS Differential linearity error ±0.25 ±0.5 LSB Gain error 1 2 3 %FS Gain drift ±5 ppm/ °C Bipolar zero error –5 ±25 mV Bipolar zero drift ±20 µV/°C Total drift ±10 ppm/ °C OUTPUT CHARACTERISTICS Voltage output(1) VREF up to 6 V, when AVDD = 6 V, AVSS = –6 V –VREF VREF V Output impedance 1 Ω Maximum output current ±25 mA CL <200 pF, RL = 2 kΩ, to 0.1% FS, 8-V step 0.65 Settling time µs To 0.003% FS 1 Slew rate(2) 35 V/ µs Code change glitch 1 LSB change around major carry 0.5 nV-S Overshoot Full-scale change 50 mV Digital feedthrough(3) 0.5 nV-S SNR Digital sine wave input, Fout = 1 kHz, 108 dB BW = 10 kHz, 2 MSPS update rate THD Digital sine wave input, Fout = 20 kHz, –72 dB 8-Vpp output, 2-MSPS update rate 0.1 Hz to 10 Hz 25 µVpp Output voltage noise At 10-kHz offset frequency 25 nV/rtHz At 100-kHz offset frequency 20 nV/rtHz Power supply rejection VDD varies ±10% 0.75 mV/V REFERENCE Large signal: 2-Vpp sine wave on 4 V DC 3 MHz Reference input bandwidth Small signal: 100-mVpp sine wave on 4 V DC 10 MHz Reference input voltage range 3 AVDD V Reference input impedance 5 k Ω Reference input capacitance 5 pF DIGITAL INPUTS VIH 0.7 x DVDD V VIL GND 0.3 x DVDD Input current ±1 µA Input capacitance 10 pF Power-on delay From VDD high to CS low 20 µs (1) Output can reach ±V DD unloaded, can reach ±(VDD– 0.2 V) for 600-Ω loading. (2) Slew rate is measure from 10% to 90% of transition when the output changes from 0 to full scale. (3) Digital feedthrough is defined as the impulse injected into the analog output from the digital input. It is measured when the DAC output does not change, CS is held high, and while SCLK and SDIN signals are toggled. 3 |
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